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cache coherence in Chinese

Pronunciation:
How to pronounce "cache coherence""cache coherence" in a sentence

Translationmobile phoneMobile

  • 高速緩存相干
  • 高速緩存一致性

Examples

  • In multiprocessors systems , cache coherence is always an important issue
    在多處理器計(jì)算機(jī)系統(tǒng)中， cache一致性一直是一個(gè)重要的問題。
  • Dividing the cache into separating tag and data arrays reduces the access time of the cache . in order to keep the cache coherence , ccu adopts moesi protocol
    Lx ? 1164具有獨(dú)立的32kb片內(nèi)數(shù)據(jù)高速緩存和32kb片內(nèi)指令高速緩存，通過ccu可以同時(shí)對(duì)指令cache和數(shù)據(jù)cache進(jìn)行查詢。
  • In this paper , we made some analysis on conventional cache coherence protocols . we provide one way to reduce remote access delay - adding a router - cache in routing components
    本文首先對(duì)常用的cache一致性協(xié)議進(jìn)行了分析，提出了一種在多處理器系統(tǒng)中減少遠(yuǎn)程訪問延時(shí)的方式一在路由部件中加入存儲(chǔ)部件一路由器cache 。
  • This policy is novel in the sense that it adopts befitting policies for different network connections with different optimization aims , and provides support for cache coherence upon transition between different situations
    該策略在不同網(wǎng)絡(luò)連接下分別采用更適合的作法，同時(shí)考慮了不同連接及斷接狀態(tài)間轉(zhuǎn)換這些特殊情況，并對(duì)緩存項(xiàng)視圖漸進(jìn)維護(hù)。
  • Then , we give some description about the working principle , organization , function of router - cache and where it should be . we also gave out a cache coherence protocol for multiprocessors systems with router - caches
    本文接著描述了路由器cache的工作原理，對(duì)其的組織、在系統(tǒng)中的位置、應(yīng)有的功能等方面進(jìn)行了討論，并設(shè)計(jì)了含有路由器cache的多處理器系統(tǒng)的cache一致性協(xié)議。
  • Smpdca architecture has six outstanding excellences : complexity of the control logics of smpdca is lower than large scale superscalar ; supplying shortest inter - processor communication latency using the shared li data cache ; no cost to maintain cache coherence ; hit rate of data cache increase ; easy to reuse many softwares of symmetric multiprocessor ( smp ) ; exploit the parallelism of applications from many levels . this paper present the architecture model of smpdca , and illustrated its function units , and discussed its key techniques , and analyzed the address image policy of multi - ported cache
    Smpdca結(jié)構(gòu)具有六個(gè)突出優(yōu)勢(shì)：相對(duì)于大規(guī)模的超標(biāo)量結(jié)構(gòu)而言， smpdca結(jié)構(gòu)的控制邏輯復(fù)雜性明顯要低得多；相對(duì)于通過共享主存來實(shí)現(xiàn)處理器之間的通信的結(jié)構(gòu)而言，通過一個(gè)共享的第一級(jí)數(shù)據(jù)cache來實(shí)現(xiàn)處理器之間的通信的smpdca結(jié)構(gòu)能夠提供非常小的處理器之間的通信延遲；沒有cache一致性維護(hù)開銷；數(shù)據(jù)cache命中率提高；便于smp (對(duì)稱多處理器結(jié)構(gòu))的軟件重用；從多個(gè)層次上開發(fā)程序的并行性。
  • She has over 14 years of experience in her broad areas of interest , including the design and performance evaluation of memory systems , cache coherence protocols , parallel i o , parallel file systems , java server performance , application server database integration , and linux performance
    她在自己感興趣的廣泛領(lǐng)域具有14年多的經(jīng)驗(yàn)，這其中包括存儲(chǔ)系統(tǒng)、高速緩存一致協(xié)議、并行i / o 、并行文件系統(tǒng)、 java服務(wù)器性能、應(yīng)用程序服務(wù)器數(shù)據(jù)庫集成和linux性能等方面的設(shè)計(jì)和性能評(píng)估。

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